Rethinking Reinforcement Learning based Logic Synthesis

Logic synthesis is an approach for finding equivalent representations of large-scale integrated circuits solved by reinforcement learning (RL) algorithms.

Image credit: Harland Quarrington via Wikimedia (OGL v1.0)

A recent paper by Huawei Noah’s Ark Lab shows that that decisions made by the RL policy do not depend on circuit features. Therefore, it is unnecessary to extract circuit features. Researchers propose a novel RL-based method which automatically recognizes critical operators and produces common operator sequences that are generalizable to unseen circuits.

Firstly, a shared policy for a number of circuits is learned. Then, a best-performing common sequence is found based on the learned policy. The evaluation shows that the proposed approach can find a common sequence, achieves good performance at delay deduction, and significantly reduces runtime.

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